Behavioral Modeling & Simulation of 2nd Order Current-Switched Charge Pump PLL Based Clock & Data Recovery Circuit

Abstract

Many digital, clock, microprocessor, and wireless gadgets employ clock and data recovery circuits (CDR). It is preferred to acquire without using a reference clock in order to save money on the receiver’s expensive crystal oscillator. In this publication, a clock and data recovery circuit (CDR) based on a 2nd-order current-switched charge-pump phase-locked loop (CSCP-PLL) is designed. No external components were used to generate the CDR. When the input data is non-zero prior to the locking point, the system enters into quasi-harmonic transient mode, and the phase error reaches a fixed value, exposing a highly chaotic region. Because the CP-PLL is a mixed-signal system consisting of analog and digital blocks as well as low and high frequencies, the linear theory of feedback system cannot be applied to sampled and non-linear characteristics. Alexander phase detector, current-switched charge-pump (CSCP), analog loop filter, and linear voltage-controlled oscillator are used to analyze the behavioral model of the CSCP-PLL-based CDR loop. Simulation results show that the clock and data are flawlessly retrieved at the intended frequencies. The findings of this research are: Total Jitter= 25.20ms, RMS Jitter= 10.25ms, Signal-to- Noise Ratio= 2.08 (unit-less), Q-Factor= 154.45 (unit-less), Rise Time= 10.80ms, Fall Time= 10.40ms, Eye-Level= -0.67 V, Vertical Opening= 0.02 V, and Horizontal Opening= 14.80ms. Also, the model comparison and validation are discussed.